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DAILY NEWS AND INFORMATION FOR THE GLOBAL GRID COMMUNITY /
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Breaking News - Networking:
Opal-RT Launches OP5000 For RT-LAB Engineering Simulators
Opal-RT Technologies Inc introduced the OP5000 range of I/O and signal
conditioning hardware, optimized for Hardware-in-the-Loop (HIL) simulation
applications. Specifically designed for use with Opal-RT's flagship RT-LAB
Engineering Simulator, the OP5000 series includes I/O interfaces based on
Field Programmable Gate Array (FPGA) technologies, and are available for
either PCI or PC/104 installation.
Based on the Virtex II processor from Xilinx Inc, FPGA I/O interfaces are at
the heart of the OP5000 series. They are designed to address I/O performance
and channel density limitations in many HIL applications, particularly where
timesteps of less than 10 microseconds are required, including modeling of
electric drives and other switched power electronic circuits. In addition, the
OP5000 series includes modules that offer advanced analog signal conversion,
with 16 simultaneous sample/hold channels with 16-bit conversion at up to 1
MHz per channel.
"Combining FPGA technologies and signal conditioning into a single product
line provides the engineer with outstanding performance and flexibility
particularly for HIL applications that require real-time simulation of dynamic
systems at very high update frequencies," said Paul Goossens, vice president
of marketing at Opal-RT Technologies Inc. "Also, the OP5000 modular signal
conditioning components bring further value to our customers by easing the
integration of the simulator into their test systems."
The OP5000 Series Product Lineup
Opal-RT's OP5000 series of products includes:
- OP5100 FPGA Reconfigurable Processing and I/O Boards that perform signal
I/O, and interface with the target PC cluster. They are internal (PCI and
PC/104 formats available) or external to the PC, communicating through its
programmable digital I/O or through the SignalWire interface.
- OP5200 Signal Conditioning and I/O (SCIO) Carriers are integrated 4U and 6U
modules that interface between the OP5100 devices and HIL system. They
incorporate signal-conditioning circuitry for voltage matching and signal
isolation, through custom circuits or a range of standardized function
modules.
- OP5300 Signal Conditioning and Conversion Modules are mounted in the OP5200
carriers and provide application-specific functionality in the HIL setup,
including signal conditioning and analog signal conversion (DAC/ADC).
In addition to the OP5000 product series' increased performance, channel
density, and potential for cost savings, the products are also programmable,
enabling the engineer to use standard FPGA software tools to configure the
product to behave according to the specific requirements of the project.
OP5000 series products can use distributed processing for I/O scheduling and
management, using direct memory transfer between the FPGA and PC processor
memory, relieving the main processors from IO-intensive tasks. The main
processors can then be dedicated to mathematical computation, which decreases
the computational time at each timestep, increasing overall system efficiency.
Programmability
OP5000 FPGA devices can be programmed exactly as required by the user, not
just the board manufacturer. Integration with Simulink and Xilinx System
Generator allows the transfer of Simulink submodels to the OP5000 FPGA
processor for distributed processing.
In addition, standard and user-developed functions can be stored on the
on-board Flash memory for instant start-up. OP5000 products are programmable
on the fly via a PCI interface or the new SignalWire communications link, and
drivers are available for QNX and RedHawk Linux for custom applications.
OP5000 PC/104 products are designed to target embedded applications, while
OP5000 PCI products, which have twice the I/O capacity of their PC/104
counterparts, target desktop and industrial PC applications.
Performance
OP5000 series products provide update rates of 100 MHz, and time-stamped
capture and generation of digital events for high precision switching of items
such as PWM I/O. I/O scheduling is performed on the OP5000 board, not on the
Target PC, so the PC processor can be dedicated to running the model,
increasing overall simulator performance.
Channel Density
OP5000 products provide up to 144 Digital I/Os on a single device, with up to
32 simultaneous 16-bit ADC and DAC channels per external I/O interface. The
modular structure of the OP5000 series allows hundreds of analog and digital
I/O channels to be incorporated through a single PCI slot. Greater channel
density and fully integrated signal conditioning dramatically reduce the
cost-per-channel for many HIL applications
SignalWire: Ultra-low-latency Inter-Processor Communication
The OP5000 series includes support for SignalWire -- a next generation network
topology that Opal-RT has developed as an alternative to IEEE 1394 for
high-performance applications. SignalWire is an inter-processor communication
technology that is optimized for real-time simulation applications. With a
latency overhead of 200 ns, it provides the computational performance needed
for applications that run at cycle times of below 10 us. Each OP5100 device is
equipped with at least one full-duplex SignalWire port enabling high-speed
data communication between each other and with the target PC cluster in the
RT-LAB Engineering Simulator.
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