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DAILY NEWS AND INFORMATION
FOR THE GLOBAL GRID COMMUNITY / OCTOBER 13, 2003: VOL. 2 NO. 41
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Breaking News -
Platforms:
Toshiba Produces Functional
Silicon Using X Architecture
The X Initiative, a semiconductor supply-chain consortium, announced that X
Initiative co-sponsor Toshiba Corporation has produced the industry's first
functional silicon for the X Architecture. The fabricated 90-nanometer (nm)
functional test chip confirms the wire-length and via reduction benefits of
the X Architecture and completes the X Initiative's roadmap for preparing the
semiconductor design chain for production fabrication of X Architecture chips.
In honor of this historic milestone and Toshiba's significant and on-going
contribution to the development of the X Architecture, the X Initiative
presented Toshiba with the "X Architecture Pioneer" award.
The X Architecture represents a new way of orienting a chip's microscopic
interconnecting wires using diagonal pathways, as well as the traditional
right-angle, or "Manhattan," configuration. By enabling designs with
significantly less wire and fewer vias (the connectors between wiring layers),
the X Architecture can provide significant, simultaneous improvement in chip
performance, power consumption and cost.
The five-metal-layer Toshiba test chip was fabricated in Toshiba's 90-nm
semiconductor process, using its standard process, equipment and materials for
this node. Compared to a Manhattan version of the same design, the X
Architecture implementation required 14 percent less total wire length and 27
percent fewer vias. The test chip is fully functional at its specified
operating frequency.
"Toshiba is very pleased to be able to present the first functional silicon
results for the X Architecture," said Takashi Yoshimori, technology executive
at Semiconductor Company, Toshiba Corporation. "We have been convinced of the
potential benefits of the X Architecture since we first became involved in its
development more than four years ago. We are very gratified to see our
investment in this new chip architecture rewarded with the positive results
from our milestone functional test chip. We are satisfied that we are ready to
go to volume production with the X Architecture in 2004."
Toshiba's functional test chip completes the pre-production
design-to-silicon
roadmap for the X Architecture laid out by the X Initiative in 2002. The focus
of the X Initiative's collaborative supply-chain preparation will now shift to
enable broad adoption of the X Architecture for production manufacturing at
both current (130nm, 90nm) and future (65nm, 45nm and below) manufacturing
nodes. First production chips are expected in 2004.
In presenting Toshiba with the X Initiative Pioneer award, Aki Fujimura, X
Initiative steering group member and chief technology officer, new business
incubation at Cadence Design Systems, Inc., noted, "Toshiba has a long track
record of innovation and investment in new technology. As co-developer of the
design technology that enables the X Architecture and co-sponsor of the X
Initiative, Toshiba has played a central role in bringing this new chip
architecture to the marketplace. The results of this first functional silicon
confirm the benefits of the X Architecture, and accelerate the adoption of the
X Architecture as a production-design option."
About the X Architecture
The X Architecture, the first production-worthy approach to the pervasive
use
of diagonal interconnect, can reduce the total interconnect, or wiring, on a
chip by more than 20 percent and via-counts by more than 30 percent, resulting
in simultaneous improvements in chip performance, power and cost. For the past
20 years, chip design has been primarily based on the de facto industry
standard "Manhattan" architecture, named for its right-angle interconnects
resembling a city-street grid. The X Architecture rotates the primary
direction of the interconnect in the fourth and fifth metal layers by 45
degrees from a Manhattan architecture. The new architecture maintains
compatibility with existing cell libraries, memory cells, compilers and IP
cores by preserving the Manhattan geometry of metal layers one through
three.
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