 |
|
DAILY NEWS AND INFORMATION
FOR THE GLOBAL GRID COMMUNITY / SEPTEMBER 8, 2003: VOL. 2 NO. 36
|
Breaking News -
Storage:
Renesas Technology Unveils 18- And
36-Megabit QDRII SRAMs
Renesas Technology America Inc, a U.S. subsidiary of the joint venture
company
of Hitachi Ltd and Mitsubishi Electric Corporation, announced a new family of
high-speed 18- and 36-Mbit Quad Data Rate-II (QDRII) SRAM devices for
high-performance network and communication system equipment such as top-end
routers and switches.
The Renesas QDRII SRAMs are built on a leading-edge 0.13-micron CMOS
process
and achieve the industry's fastest speeds: 250MHz for 2-word burst devices and
333MHz for 4-word burst types in both capacities. When used as buffer memory,
these fast SRAMs provide very high bandwidths, as high as 1.33 Gigabytes per
second. This performance allows the design of communication and network
equipment that can successfully manage very high volumes of traffic.
Meeting The Need For Greater Bandwidth
"In today's networking environment, transmission speeds of communication
equipment are quickly exceeding 10Gbits per second," said Mark D'Arcangelo,
product marketing manager of SRAM products at Renesas. "Renesas' new QDRII
SRAMs enable our customers to market products that handle the OC-192 data
rates needed today, while also helping them migrate to designs for the
40Gbit per second rates that OC-768 links can deliver."
The Renesas QDRII SRAMs, members of the HM66AQB family, offer highly
desirable
features not available in conventional synchronous SRAMs. The QDRII memory
devices provide two data ports that operate independently at Double Data Rate
(DDR), so they can output four data words per clock cycle. Their data-valid
window is wide -- 65 percent of the clock cycle -- to minimize timing problems
even during full-speed operation. Also, their echo-clock signals help simplify
data capture by ensuring a precise and stable relationship to data-valid
timing. System engineers can take advantage of these additional features,
among others, to maximize the bandwidth of data-intensive networking and
communication designs.
Compliant To The QDRII Standard
The new devices are fully compliant with the second-generation, QDRII/DDRII
SRAM electrical and mechanical specifications defined by the members of the
QDR Consortium, which is online at http://www.qdrsram.com . The QDR interface
has been adopted by the Network Processing Forum as one of the key elements in
Phase I of the Look-Aside Interface (LA-1). The LA-1 Interface is a critical
specification that is designed to offload certain tasks from the Network
Processing Unit of telecommunication equipment.
The Renesas QDRII family devices comprise of x8, x9, x18 and x36
organizations; 2-and 4-word burst capabilities and various speed ratings. All
operate from a 1.8V power source (VDD), use HSTL I/Os, and have the requisite
QDRII package and pinout: a 165-pin, 15mm x 17mm fine-pitch ball
grid array (FBGA). Device datasheets are available at our Web site at
www.renesas.com/eng/p
roducts/memory.
To expand this product line, Renesas is currently developing 18- and
36-Mbit
DDRII SRAMs. Sample shipments of the 18-Mbit DDRII devices are scheduled for
the second quarter of 2004 and 36-Mbit devices in January.
|