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DAILY NEWS AND INFORMATION
FOR THE GLOBAL GRID COMMUNITY / SEPTEMBER 8, 2003: VOL. 2 NO. 36
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Breaking News -
Platforms:
IBM And UT-Austin To Work On
Single-Chip Supercomputer
The University of Texas-Austin and IBM Research, based on support from the
Defense Advanced Research Projects Agency, will collaborate to produce an
adaptive, high-performance microprocessor that could revolutionize computing.
The university team has conceived a new architecture, called TRIPS (Tera-op
Reliable Intelligently-adaptive Processing System), that is designed to
provide supercomputer performance on a single chip. Researchers at IBM's
Austin Research Lab are working closely with the UT-Austin team to develop a
number of the relevant technology innovations necessary to realize such
systems, and engagements are underway to ultimately commercialize the
results.
The TRIPS architecture is designed to provide supercomputer performance on
a
single chip, ultimately scaling to deliver more than one trillion operations
per second by 2010. In addition, the system will offer unprecedented
flexibility to work well with many different types of software applications
including desktop, signal processing, graphics, server and scientific
applications. This flexibility may allow a single TRIPS chip to serve several
different processor markets, instead of current approaches that use unique and
specialized processors for each market.
The fundamental innovation in the TRIPS design is its "block-oriented
execution." Instead of operating on only a few computations at a time, the
TRIPS processor operates on large blocks of computations mapped to an array of
execution units on the chip. This approach allows many more instructions to
execute in parallel, thus offering higher performance. These computation
arrays include support for "polymorphism," which adapts them to match the type
of software application currently running on the hardware. The IBM Research
team is focused on the optimization of commercial computing applications for
this novel architecture. The IBM team is also exploring new circuit and chip-
design methodology innovations to enable this class of highly-configurable
future chips.
The team will work for 30 months to develop a prototype microprocessor and
system containing up to four processor cores, each capable of executing 16
operations per clock cycle, and a uniquely partitioned cache structure
designed to offer higher performance than traditional approaches. The chip
will contain over 250 million transistors, and will operate at 500 MHz. The
goal is to demonstrate the feasibility of a full-scale industrial development
that could offer a 10 GHz chip capable of executing over a trillion
instructions per second. The joint UT-Austin/IBM Research team is consulting
with IBM Microelectronics on initial chip-design considerations, and it is
expected that IBM Microelectronics will be the physical-design and fabrication
partner for the TRIPS chip.
This research collaboration is being facilitated by an IBM Shared
University
Research (SUR) Award of a Linux-based IBM eServer xSeries computing cluster,
which will help provide the bandwidth and computational capabilities required
to accurately simulate and verify the advanced TRIPS processor design. The
Linux cluster also will enable researchers to model large server workloads
running on a multi-chip TRIPS system, improving the understanding of system-
level design requirements of diverse supercomputing environments. IBM's SUR
program awards computing equipment to colleges, universities and institutions
of higher education around the world to facilitate research projects in areas
of mutual interest.
Construction of the TRIPS prototype system is supported by a total of $11.1
million in funding from DARPA. UT-Austin scientists expect to have TRIPS
prototype chips and systems running in their laboratory by December 2005.
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