Breaking News -
Networking:
Actel Introduces New UTOPIA IP
Cores
Actel Corporation announced the addition of three intellectual property
(IP)
building blocks that have been optimized for use with the company's
reprogrammable, flash-based ProASIC Plus and high-speed, antifuse-based
Axcelerator field-programmable gate arrays (FPGAs). Developed, verified and
supported by Actel, the new UTOPIA CoreU1LL, CoreU1PHY and CoreU2PHY
DirectCores are targeted at asynchronous transfer mode (ATM) communication
system developers for their next-generation ATM local area network (LAN) and
ATM over SONET/SDH applications, as well as virtual private networks (VPN),
frame-relay backbones and residential broadband networks.
"Many ATM system designers today are using Actel's low-cost ProASIC Plus
and
high-speed Axcelerator FPGAs because they offer maximum design security and
help the system developer quickly enter the market," said Yankin Tanurhan,
senior director, IP solutions, Actel Corporation. "The combination of our
FPGAs with the new UTOPIA IP cores gives communications designers ready access
to low-cost building blocks for well-defined, standard functions, while
providing the ability to uniquely customize a portion of the device for their
application."
New IP Cores for Actel FPGAs
The CoreU1LL link-layer (master) interface and CoreU1PHY physical-layer
(slave) interface cores conform to the ATM Forum's UTOPIA Level 1
specification (version 2.01) and support 8-bit operation at 25 MHz. Both
include separate transmit and receive clocks and interface pins that can be
used individually or combined to form a complete UTOPIA transceiver.
Utilization for the CoreU1LL and CoreU1PHY is less than 10 percent of the
company's smallest ProASIC Plus and Axcelerator devices, leaving FPGA area for
multiple CoreU1 cores or additional user logic.
The CoreU2PHY core conforms to the ATM Forum's UTOPIA Level 2 specification
(version 1.0) and supports 16-bit operation at 50 MHz. As with the CoreU1LL
and the CoreU1PHY, the CoreU2PHY includes separate transmit and receive clocks
and interface pins. Additionally, CoreU2PHY supports one MPHY address in
single-PHY mode or up to 32 MPHY addresses in multiple-PHY mode.
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