Breaking News -
Security:
RISC Microprocessor From Toshiba
Has Built-In Encryption
Toshiba America Electronic Components Inc (TAEC) announced a new 64-bit MIPS-
based RISC microprocessor (MPU) that brings high-level security to data
transmissions in all high-performance packet processing applications. The new
MPU supports the data encryption standard (DES) algorithm, the most widely
used encryption standard, and achieves highly secure data transfers in various
networking and communications applications. "Data protection is one of the
most serious challenges that networking and communications system providers
are facing," said Farhad Mafie, vice president of the ASSP Business Unit at
TAEC. "It is no small task to maintain the confidentiality and integrity of
information during transmission over the Internet or Intranet. Toshiba has
addressed this problem by offering a high-performance, highly-integrated 64-
bit MIPS-based RISC networking/communications processor that has a built-in
DES engine."
The new microprocessor, TMPR4926XB-200, is based on a TX49/H2 core operating
at 200 megahertz (MHz). Its design integrates Toshiba's TMPR4925XB-200 CPU
with a dedicated DES algorithm in a single chip, allowing use of the
TMPR4925XB-200's software and development environment. The MPU supports a wide
range of applications with built-in controllers for peripheral component
interconnect (PCI), direct memory access (DMA) and NAND flash memory.
"Toshiba's TMPR4926XB processor provides a complete system solution for
networking and communications equipment," said Tetsuro Wada, director of
Platform Development of the ASSP Business Unit at TAEC. "A high-performance
64-bit MIPS RISC core has been coupled with carefully selected peripherals to
meet these system requirements. The high-performance DES engine provides
hardware encryption and decryption without loading the central processing unit
with software emulation overhead. This is a key system performance
advantage."
Market Background
As broadband Internet connections become prevalent, more and more companies
are promoting private data networks as a vehicle for electronic business.
Virtual Private Networks use the public telecommunications infrastructure but
maintain privacy by using a tunneling protocol and security procedures. This
approach necessitates high-level encryption, a requirement that Toshiba meets
with the new processor. Secure data transmission first encrypts data to be
transmitted, turning it into unintelligible code, and decrypts it into its
original form on receipt. In such a system, security depends on the security
of the key used to encode and decode the data. Although the encryption
algorithm specified in the DES algorithm is common, a unique key for each
transaction protects the security of data. Encrypted data can be deciphered
only by using a key identical to that used to encipher it. Even if
unauthorized recipients of enciphered data have access to the DES algorithm,
they cannot access original data without the correct key.
Key features of the microprocessor include:
- Integration of DES circuitry supports the design of network equipment for
VPN. In order to enhance the security level, DES-cipher block mode (CBC) can
be supported by adding triplicate DES and a feedback loop.
- A standard built-in Peripheral Component Interconnect (PCI) bus
interface allows the new microprocessor to interface with Toshiba's TC86C001FG
companion chip, which integrates support for six key controllers: PCI bus, AT-
Attachment (ATA), ATA Packet Interface (ATAPI), Universal Serial Bus (USB)
host, USB device and Inter-IC (I2C) bus. In home servers and home gateways,
built-in hard disk drives are a potential application.
- The NAND flash memory controller supports design of digital consumer
and network equipment and eliminates external components.
Pricing and Availability
Samples of TMPR4926XB-200 are now available at $28/piece in 10,000-piece
quantities. Mass production is slated to begin in October 2002 at 100,000
units per month.
Technical Specification Summary
- Part Number -- TMPR4926XB-200
- Instruction Cache -- 16 kilobytes (Kbytes)
- Data Cache -- 16Kbytes
- Power Supply -- 1.5 Volts (V) internal, 3.3V input/output
- Maximum Operating Frequency -- 200MHz internal, 80MHz external bus at 32-
bit width
Built-in Peripherals
- Synchronous dynamic random access memory (SDRAM) controller (4
channels: SDRAM/SyncFlash)
- External bus controller (6 channels: read only memory/static random
access memory/ I/O device)
- PCI controller (4 channels, 33MHz at 32-bit width)
- DMA controller (4 channels)
- NAND Flash memory controller
- DES circuit
- AC-Link controller (audio and modem codec)
- PCMCIA interface (2 slots)
- Synchronous serial interface (serial peripheral interface) Package
- Plastic ball grid array-256-pin
About TAEC
Combining quality and flexibility with design engineering expertise, TAEC
brings a breadth of advanced, next-generation technologies to its customers.
This broad offering includes semiconductors, flash memory-based storage
solutions, optical communication devices, displays and rechargeable batteries
for the computing, wireless, networking, automotive and digital consumer
markets. TAEC is an independent operating company owned by Toshiba America,
Inc., a subsidiary of Toshiba, the second largest semiconductor company
worldwide in terms of global sales for the year 2001 according to
Gartner/Dataquest's Worldwide Semiconductor Market Share Ranking. Toshiba is a
world leader in high-technology products with more than 300 major subsidiaries
and affiliates worldwide.
chips.toshiba.com
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